MCT8317A datasheet(116/161 Pages) TI1

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Table 8-31. FAULT_CONFIG2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-2

ABN_LOCK_SPD_RATIO R/W

Ratio of electrical speed between two consecutive cycles above

which abnormal speed lock fault is triggered

0h = 2

1h = 4

2h = 6

3h = 8

1-0

ZERO_DUTY_THR

R/W

Duty cycle below which target speed is zero

0h = 0%

1h = 1%

2h = 2.0%

3h = 2.5%

8.7.3 Hardware_Configuration Registers

Table 8-32 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset

addresses not listed in Table 8-32 should be considered as reserved locations and the register contents should

not be modified.

Table 8-32. HARDWARE_CONFIGURATION Registers

Offset

Acronym

Section

A6h

PIN_CONFIG1

Hardware pin configuration

Section 8.7.3.1

A8h

PIN_CONFIG2

Hardware pin configuration

Section 8.7.3.2

AAh

DEVICE_CONFIG

Peripheral configuration

Section 8.7.3.3

Complex bit access types are encoded to fit into small table cells. Table 8-33 shows the codes that are used for

access types in this section.

Table 8-33. Hardware_Configuration Access Type

Codes

Access Type

Code

Description

Read Type

Read

Write Type

Write

Reset or Default Value

-n

Value after reset or the default

value

MCT8317A

SLLSFQ2 – JANUARY 2023

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