HC05V7GRSSLASHD datasheet(148/170 Pages) NXP

148 / 170 page

SECTION 16: INSTRUCTION SET

Page 134

MC68HC05V7 Specification Rev. 1.0

16.3

BRANCH INSTRUCTIONS

This set of instructions branches if a particular condition is met; otherwise, no operation is

performed. Branch instructions are 2-byte instructions. Refer to the following list for branch

instructions.

16.4

BIT MANIPULATION INSTRUCTIONS

The MCU is capable of setting or clearing any read/write bit that resides in the first 256

bytes of the memory space where all port registers, port DDRs, timer, timer control, and on-

chip RAM reside. An additional feature allows the software to test and branch on the state

of any bit within these 256 locations. The bit set, bit clear, and bit test and branch functions

are each implemented with a single instruction. For test and branch instructions, the value

Function

Mnemonic

Increment

INC

Decrement

DEC

Clear

CLR

Complement

COM

Negate (Two’s Complement)

NEG

Rotate Left Thru Carry

ROL

Rotate Right Thru Carry

ROR

Logical Shift Left

LSL

Logical Shift Right

LSR

Arithmetic Shift Right

ASR

Test for Negative or Zero

TST

Function

Mnemonic

Branch Always

BRA

Branch Never

BRN

Branch if Higher

BHI

Branch if Lower or Same

BLS

Branch if Carry Clear

BCC

Branch if Higher or Same

BHS

Branch if Carry Set

BCS

Branch if Lower

BLO

Branch if Not Equal

BNE

Branch if Equal

BEQ

Branch if Half Carry Clear

BHCC

Branch if Half Carry Set

BHCS

Branch if Plus

BPL

Branch if Minus

BMI

Branch if Interrupt Mask Bit is Clear

BMC

Branch if Interrupt Mask Bit is Set

BMS

Branch if Interrupt Line is Low

BIL

Branch if Interrupt Line is High

BIH

Branch to Subroutine

BSR

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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