전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

HC705V8GRS/D 데이터시트(PDF) 37 Page - NXP Semiconductors

부품명 HC705V8GRS/D
상세설명  The Motorola MC68HC705V8 microcontroller is a custom HC05 based MCU featuring a Message Data Link Controller (MDLC) module and on-chip power regulation.
PDF  172 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705V8GRS/D 데이터시트(HTML) 37 Page - NXP Semiconductors

Back Button HC705V8GRS/D Datasheet HTML 33Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 34Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 35Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 36Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 37Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 38Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 39Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 40Page - NXP Semiconductors HC705V8GRS/D Datasheet HTML 41Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 37 / 172 page
background image
SECTION 3: EPROM AND EEPROM
Page 26
MC68HC705V8 Specification Rev. 2.1
which will therefore represent the value transferred from the MOR at reset if it is left
unprogrammed.
.
Figure 3-3:
Option Register
REGEN - Regulator Enable or Disable
1 = internal voltage regulator is enabled.
0 = internal voltage regulator is disabled.
COPEN - COP Timer Enable or Disable
1 = COP timer enabled.
0 = COP timer disabled.
IRQ - Interrupt Request Pin Sensitivity
1 = IRQ pin is both negative edge and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
LVR - Low Voltage Reset Enable or Disable
1 = LVR enabled
0 = LVR disabled
STOPEN - Enable the entry into STOP mode via the execution of the STOP
instruction.
1 = STOP mode enabled
0 = STOP mode disabled. If STOP instruction is executed, a chip reset will result.
MDLCPU - Enable the MDLC BUS pin to power up the on board regulator on a rising
edge
1 = enable
0 = disable
VDDC - VDD Clamp. When this option is enabled and the on board regulator has been
disabled through software, the VDD pin will be clamped to VSS through an
active device.
1 = enable
0 = disable
-
VDDC
MDLCPU
LVR
STOPEN
IRQ
COPEN
REGEN
$3C00
0
000000
0
ERASED:
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com