HC705V8GRSSLASHD datasheet(98/172 Pages) NXP

98 / 172 page

SECTION 13: PULSE WIDTH MODULATOR

Page 87

MC68HC705V8 Specification Rev. 2.1

Reads of this register will always result in the read of the PWM Data Register and not the

buffer.

Upon RESET the user should write to the data register prior to enabling the PWM system

(for example, prior to setting the PSA and PSB bits for PWM input clock rate). This will avoid

an erroneous duty cycle from being driven. During regular user mode the user should write

to the PWM Data data register after writing the PWM Control Register.

Figure 13-4:

PWM Write Sequences

13.2.1

PWM CONTROL

Figure 13-5:

PWM Control Register

PSA1, PSA0, PSB3-PSB0- PWM Clock Rate

These bits select the input clock rate and determines the period, as shown in Table 13-1.

Note that some output frequencies can be obtained with more than one combination of PSA

and PSB values. For instance a PWM output of E/512 can be obtained with either

PSA1:PSA0 = 10 and PSB3-PSB0 = 0001 or PSA1:PSA0 = 01 and PSB3-PSB0 = 1000.

This scheme allows for 38 unique frequency selections.

Table 13-1:

PWM Clock Rate

PSA1:PSA0

PSB3-PSB0

RCLK

SCLK

PWM OUT

xxxx

off

0000-1111

fosc/1

fosc/1-fosc/16

fosc/64-

fosc/1024

0000-1111

fosc/8

fosc/8-fosc/128

fosc/512-

fosc/8192

0000-1111

fosc/16

fosc/16-fosc/

256

fosc/1024-

fosc/16384

Initialize PWM Data 0

Write PWM CONTROL

OR RESET

POR

Write PWM CONTROL

Write PWM Data 1

PSA1

PSB2

PSB1

PSB0

PSA0

$31

0000

RESET:

PSB3

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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