STM32H7B0AB datasheet(89/205 Pages) STMICROELECTRONICS

89 / 205 page

Symbol

Parameter

Conditions

Typ(1) Max(1)(2)

Unit

tWUDSTOP2(3)

Wakeup from DStop2, clock kept

running

SVOS3 LP, CSI, flash memory in low-power mode

µs

51.3

SVOS4, CSI, flash memory in low-power mode

62.0

SVOS5, CSI, flash memory in low-power mode

77.3

tWUSTDBY(3)

Wakeup from Standby mode

257

330

1. Guaranteed by characterization results.

2. Measures done at −40 °C in the worst conditions.

3. The wakeup times are measured from the wakeup event to the point in which the application code reads the first instruction.

6.3.9

External clock source characteristics

High-speed external user clock generated from an external source

In bypass mode, the HSE oscillator is switched off and the input pin is a standard I/O.

The external clock signal has to respect Table 45. High-speed external user clock characteristics in addition to

Table 63. I/O static characteristics. The external clock can be low-swing (analog) or digital. In case of a low-swing

analog input clock, the clock squarer must be activated (refer to RM0455).

Table 45. High-speed external user clock characteristics

Symbol

Parameter

Conditions

Min(1)

Typ(1)

Max(1)

Unit

fHSE_ext

User external clock source

frequency

External digital/analog

clock

MHz

VHSEH

Digital OSC_IN input high-

level voltage

External digital clock

0.7 VDD

VDD

VHSEL

Digital OSC_IN input low-level

voltage

VSS

0.3 VDD

tW(HSEH)/tW(HSEL)(2)

Digital OSC_IN input high or

low time

External digital clock

VlswHSE

(VHSEH−VHSEL)(3)

Analog low-swing OSC_IN

peak-to-peak amplitude

External analog low-

swing clock

0.2

2/3 VDD

DuCyHSE

Analog low-swing OSC_IN

duty cycle

tr(HSE)/tf(HSE)

Analog low-swing OSC_IN rise

and fall times

External analog low-

swing clock, 10% to 90%

0.05 / fHSE_ext

0.3 / fHSE_ext

1. Guaranteed by design.

2. The rise and fall times for a digital input signal are not specified. However the VHSEH and VHSEL conditions must be fulfilled.

3. The DC component of the signal must ensure that the signal peaks are located between VDD and VSS.

STM32H7B0xB

Operating conditions

DS13196 - Rev 7

page 89/205

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