| 전자부품 데이터시트 검색엔진 |
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VNF1048F 데이터시트(PDF) 19 Page - STMicroelectronics |
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VNF1048F 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 52 page ![]() VDS Detection Self Test result is the difference between converted value obtained during Self Test execution and the value already stored in SR#4 (VDS field), corresponding to the normal measurement performed during operation; such delta measure result is stored in SR#5 (S_T_VDS field) together with the Self Test status. During Self Test execution it is also possible to emulate external FET VDS fault condition by playing with programmable thresholds available through register CR#2 (VDS_THR field); fault emulation result is stored in SR#5 (S_T_VDS_MAX1 bit field). To be noted that diagnostic fault for normal operation (VDS_MAX, SR#1) is inhibited during execution, while all the others are kept enabled. The transition from Self Test state to Unlocked state is automatically guaranteed after the test is completed (around 10 μs) or if the test is stopped through S_T_STOP = 1 (Self Test aborted). The transition from the Self Test state to the Locked state can occur in case of watchdog timeout or HWLO = 1 (Self Test aborted). Figure 7. VDS monitor self test flow sequence VNF1048F External FET VDS Detection Self Test DS13084 - Rev 6 page 19/52 |
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