VNF1048F datasheet(33/52 Pages) STMICROELECTRONICS

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Address

Name

Access

Content

Comments

13h

WD bit pos. 1

Read Only

43h

Bit7,WB1 = 0

Bit6,WB2 = 1

WBA[5-0], Bit[5-0] = address of the config. register, where the WD bit is

located = 03h = 000011b

14h

WD bit pos. 2

Read Only

C1h

Bit7,WB1 = 1

Bit6,WB0 = 1

Bit position of the WD bit within the corresponding configuration register

= 01d = 000001b

3Fh

Advanced

Operation Code

Read Only

00h

Access to this address provokes a SW reset (all control registers are

set to their default values; in addition, all clearable status registers are

cleared too).

Note:

data field should not be “all ones”, otherwise an “SDI stuck

at” error occurs.

6.13

Control registers

Table 35. CR#1: Control Register 1 (read/write); Address 01h (ID 13.1)

Bit

Default

Name

Description

23 ÷ 12

Unused

GOSTBY

GOSTBY can be set to 1 only if UNLOCK = 1; trying to set this bit to 1 when UNLOCK = 0

will have no effects and it will maintain its previous value.

GOSTBY can be reset to 0 also when UNLOCK = 0.

To send a GOToStandby sequence it is necessary to send two consecutive SPI frames, as

follows:

1st SPI write operation to set UNLOCK bit to 1

2nd SPI write operation to set GOSTBY bit to 1 and EN bit to 0.

A transition to Standby state causes GOSTBY to be reset to 0.

EN can be set to 1 only if UNLOCK = 1; trying to set this bit to 1 when UNLOCK = 0 will

have no effects and it will maintain its previous value.

EN can be reset to 0 also when UNLOCK = 0.

To send a GOToUnlocked sequence it is necessary to send two consecutive SPI frames as

follows:

1st SPI write operation to set UNLOCK bit to 1

2nd SPI write operation to set GOSTBY bit to 0 and EN bit to 1.

A transition to Unlocked state causes EN to be set to 1.

A transition to Locked state causes EN to be reset to 0.

S_T_START

When it is set to 1, starts selected self-test.

If current state is Unlocked and S_T_CFG is not 000, then setting this bit causes a transition

to Self-Test state.

This bit is automatically reset.

S_T_STOP

When it is set to 1, stops execution of selected self-test.

This bit is automatically reset.

7 ÷ 5

000

S_T_CFG

Self Test selection:

000: No selection

001: Current sense

VNF1048F

Control registers

DS13084 - Rev 6

page 33/52

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