VNF1048F datasheet(3/52 Pages) STMICROELECTRONICS

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Table 1. Pin functions

Name

Function

Input supply pin. Connect to the 12 V, 24 V, 48 V battery voltage.

Charge pump output.

CP2P

Charge pump–Positive terminal of the flying capacitor CP2.

CP2M

Charge pump–Negative terminal of the flying capacitor CP2.

CP1P

Charge pump–Positive terminal of the flying capacitor CP1.

CP1M

Charge pump–Negative terminal of the flying capacitor CP1.

GND

Ground connection.

VSPI

DC supply input for the SPI interface. 3.3 V and 5 V compatible.

V3V3

Output of the 3.3 V internal LDO voltage regulator (logic and I/O supply).

Connect a low ESR capacitor (1 μF) close to this pin.

CSN

Chip select not (active low) for SPI communication. It is the selection pin of the device. CMOS compatible input.

SDI

Serial data input for SPI communication. Data is transferred serially into the device on SCK rising edge.

SDO

Serial data output for SPI communication. Data is transferred serially out of the device on SCK falling edge.

SCK

Serial clock for SPI communication. It is a CMOS compatible input.

DIAG

Open drain logic output. Diagnostic feedback. DIAG = '0' if (SR1.WAKEUPM = '1') or (GSB.DIAGS = '1') or

(GSB.DE = '1') else '1'

HWLO

Active high input pin compatible with 3.3 V and 5 V CMOS; it causes transitions to states where the registers are

locked from writing.

ISNS_P

Current sense amplifier positive input.

ISNS_N

Current sense amplifier negative input.

HS_GATE Output of the gate driver for the external FET.

OUT

External FET source connection.

NTC

Positive input pin for external NTC resistor.

NTC_M

Negative input pin for external NTC resistor.

TEST1

Test mode pin 1- must be connected to ground.

TEST2

Test mode pin 2- must be connected to ground.

VNF1048F

Block diagram and pin description

DS13084 - Rev 6

page 3/52

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