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VNF1048F 데이터시트(PDF) 28 Page - STMicroelectronics

부품명 VNF1048F
상세설명  High-side switch Controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications
PDF  52 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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VNF1048F 데이터시트(HTML) 28 Page - STMicroelectronics

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6.6
Read mode
The read mode of the device allows to read and to check the state of any registers.
Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first.
Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of
the serial clock (SCK). The first byte corresponds to the Global Status Byte, second, third and forth byte to the
content of the addressed register.Unused bits will be always read as 0.
In order to avoid inconsistency between the Global Status byte and the Status register, the Status register
contents are frozen during SPI communication.
Figure 11. SPI read operation
0
1
SDI
SDO
CSN
(24 bits)
Data
MSB
MSB
LSB
LSB
MSB Address
(8bit)
Global Status Byte
Command Byte
LSB
LSB
MSB
GADG1010171333PS
Don’t care
(24 bits)
6.7
Read and clear status command
The read and clear status operation is used to clear the content of the addressed status register (see
Table 33. RAM memory map (ID 12.1)). A read and clear status operation with address 0x3Fh clears all Status
registers simultaneously.
Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. The command byte allows to
determine which register content is read and the payload bits set to 1 into the data byte determine the bits into the
register which have to be cleared.
Outgoing data are shifted out MSB first on the falling edge of the CSN pin and others on the falling edge of the
serial clock (SCK). The first byte corresponds to the Global Status byte, second, third and forth byte to the content
of the addressed register. Unused bits will be always read as 0.
In order to avoid inconsistency between the Global Status byte and the Status register, the Status register
contents are frozen during SPI communication.
Figure 12. SPI read and clear operation
CSN
SDI
SDO
Global Status byte
MSB
LSB
Data byte
MSB
LSB
Command byte
MSB
Address
LSB
1
0
Data byte
Read and clear status
operation
MSB
LSB
(8 bits)
GADG1010171505PS
(24 bits)
(24 bits)
VNF1048F
Read mode
DS13084 - Rev 6
page 28/52



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