STUW81300 datasheet(27/63 Pages) STMICROELECTRONICS

부품명	STUW81300

상세설명	Wideband RF/microwave PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs

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제조업체	STMICROELECTRONICS [STMicroelectronics]

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27 / 63 page

DS11314 Rev 7

27/63

STuW81300

Circuit description

7.5

Phase frequency detector (PFD)

The PFD takes inputs from the reference and the VCO dividers and produces an output

proportional to the phase error. The PFD includes a delay gate that controls the width of the

anti-backlash pulse (1.2 to 3 ns). This pulse ensures that there is no dead zone in the PFD

transfer function.

Figure 23 shows a simplified schematic of the PFD.

Figure 23. PFD diagram

7.6

Lock detect

The lock detector indicates the lock state for the PLL. The lock condition is detected by

comparing the UP and DOWN outputs of the digital phase frequency detector.

A CMOS logic output signal indicates the lock state. The polarity of the output signal can be

inverted using the LD_ACTIVELOW bit.

The lock condition occurs when the delay between the edges of UP and DOWN signals is

lower than a specific value (3-bit programmable from 2 ns to 16 ns) and this condition is

stable for a specific number of consecutive PFD cycles (3-bit programmable counter from 4

to 4096 cycles).

This extreme flexibility is needed for the lock detector circuitry to work properly with all

possible PLL setups (Integer-N, Fractional-N, different PFD frequencies and so on).

MsV43273V1

STUW81300 데이터시트(PDF) 27 Page - STMicroelectronics