STUW81300 datasheet(34/63 Pages) STMICROELECTRONICS

부품명	STUW81300

상세설명	Wideband RF/microwave PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs

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제조업체	STMICROELECTRONICS [STMicroelectronics]

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34 / 63 page

Circuit description

STuW81300

34/63

DS11314 Rev 7

The Data bits are stored in the internal shift register on the rising edge of SCK.

The first bit, CO is used for mode selection (0=Write Operation, 1=Read Operation). The

bits A[3:0] represent the register address, and D[26:0] are the data bits.

In some registers, the first data bit, D26, is used (when set to ‘1’) for double-buffering

purposes. In this case the register content is stored in a temporary buffer and is transferred

to the internal register once a write operation is done on the master register ST0.

Figure 25. SPI timing diagram

MsV43275V1

Tsetup Thold

SDI

LD_SDO

SCK

MSB

MSB - 1

LSB

Tcd

Tdi

Tck

Tec

Table 9. SPI timings

Parameter

Comments

Min

Typ

Max

Unit

Tsetup

Data to clock setup time

Thold

Data to clock hold time

Tck

Clock cycle period

Tdi

Disable pulse width

Tcd

Clock-to-disable time

Tec

Enable-to-clock time

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