STUW81300 datasheet(32/63 Pages) STMICROELECTRONICS

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Circuit description

STuW81300

32/63

DS11314 Rev 7

7.12

Low-power functional modes

All the performance characteristics defined in the electrical specifications are achieved in full

current mode. The STuW81300 provides a set of low power functional modes to allow

control of the current consumption of the different blocks.

This feature combined with the use of a 3.3 V regulated voltage for pins #3, 16, 32, can be

helpful for applications requiring low power consumption. The power saving modes trade

the current consumption with the phase-noise performance and/or output level.

7.13

LDO voltage regulators

Low drop-out (LDO) voltage regulators are integrated to provide the synthesizer with stable

supply voltages against input voltage (VIN), load and temperature variations. Five regulators

are included to ensure proper isolation among circuit blocks. These regulators are listed

below along with the target specifications for the regulated output voltage (Vreg) and current

capability:

•

LDO_DIG (to supply the digital circuitry),

Vreg = 2.6 V, Imax = 50 mA, VIN range: 3.0 to 5.4 V

•

LDO_PLL (to supply the PLL),

Vreg = 2.6 V, Imax = 50 mA, VIN range: 3.0 to 5.4 V

•

LDO_RF (to supply the RF blocks),

Vreg = 2.6 V, Imax = 100 mA, VIN range: 3.0 to 5.4 V

•

LDO_VCO (to supply the low-voltage VCO sub-blocks):

Vreg = 2.6 V, Imax = 100 mA, VIN range: 3.0 to 5.4 V

•

LDO_4V5 (to supply high-voltage sub-blocks):

Vreg = 4.5 V and 3.3 V programmable, Imax = 150 mA

VIN range: 3.6 to 5.4 V (when Vreg = 3.3 V)

VIN range: 5.0 to 5.4 V (when Vreg=4.5 V)

Proper stability and frequency response are achieved by connecting 10 µF load capacitors

at the regulated output pins. The optimal configuration is achieved by connecting a small

resistor in series with the capacitor in order to guarantee the controlled ESR required to

ensure the proper phase margin, together with the best performance in terms of noise and

PSRR. For a complete view of required connections and component values associated with

the LDO output pins, see the related PCB schematics section available from the

STuW81300 product page on the ST website.

Very-low noise requirements have been assumed for the design of the VCO-related

regulators (LDO_VCO and LDO_4V5). To comply with the noise specifications, these LDOs

exploit an additional external bypass (feed forward) capacitor of 100 nF.

All LDOs include over-current protection to avoid short-circuit failures, as well as internal

power ramping to minimize startup current peaks.

All LDOs operate from a reference voltage of 1.35 V, which is internally generated by an

integrated band-gap circuit and noise-filtered through an external 10 µF capacitor.

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