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DA16200 데이터시트(PDF) 66 Page - Renesas Technology Corp |
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DA16200 데이터시트(HTML) 66 Page - Renesas Technology Corp |
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66 / 154 page ![]() DA16200 Ultra Low Power Wi-Fi SoC Datasheet Revision 3.6 04-Jan-2023 CFR0011-120-00 66 of 153 © 2023 Renesas Electronics Table 50: I2S Transmit Timing Parameters Description Timing Min Typ Max Unit I2S_BCLK frequency fBCLK - 3.072 MHz High period of the BCLK clock T2 - ½ fBCLK ns Low period of the BCLK clock T3 - ½ fBCLK ns I2S_SDO output hold (falling edge) T4 160 - ns I2S_SDO output hold (rising edge) T5 160 - ns Table 51: I2S Receive Timing Parameters Description Timing Min Typ Max Unit I2S_BCLK frequency fBCLK - 3.072 MHz High period of the BCLK clock T2 - ½ fBCLK ns Low period of the BCLK clock T3 - ½ fBCLK ns I2S_SDO input setup time T4 15 - ns I2S_SDO input hold time T5 60 - ns |
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