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DA16200

Ultra Low Power Wi-Fi SoC

Datasheet

Revision 3.6

04-Jan-2023

CFR0011-120-00

73 of 153

9.10.3

Baud Rate

The UART clock frequency (FUARTCLK) is fixed at 80 MHz. The Baud Rate Divisor can be

calculated as (FUARTCLK / (16 x Baud Rate)). The Baud Rate Divisor is comprised of the integer

part (UART_INTBRDIV) and fractional part (UART_FRABRDIV). The maximum baud rate of

DA16200 UART is 2.5 MBaud.

The example below shows how to calculate the divisor value.

If the required baud rate is 921600 with 80 MHz FUARTCLK, the Baud Rate Divisor becomes:

(8 x 107) / (16 x 921600) = 5.425.

This means that the integer value is 5 and the fractional value is 0.425.

Then, the fraction part becomes integer ((0.425 x 64) + 0.5) = 27.

Then, the generated baud rate divider is 5 + 27/64 = 5.422.

Finally, the generated baud rate becomes (8 x 107) / (16 x 5.422) = 922169.

And the error between the required baud rate and the generated baud rate is:

(922169

– 921600) / 921600 x100 = 0.062 %

9.10.4

Hardware Flow Control

The hardware flow control feature is fully selectable, and serial data flow is controlled by using

nUARTRTS output and nUARTCTS input signals. Figure 53 shows how two different UARTs can

communicate using hardware flow control.

Figure 53: UART Hardware Flow Control

When RTS flow control is enabled, nUARTRTS signal is asserted until the receive FIFO is filled up to

programmed level. When CTS flow control is enabled, the transmitter can transmit the data when the

nUARTCTS signal is asserted. CTSEn (CTS enable) and RTSEn (RTS enable) bits are determined

by 14th (RTS) and 15th bit (CTS) of UARTCR register.

Table 54: Control Bits to Enable and Disable Hardware Flow Control

CTSEn

RTSEn

Description

Both RTS and CTS flow control are enabled

Only CTS flow control is enabled

Only RTS flow control is enabled

Both RTS and CTS flow control are disabled

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