P9221-R3 datasheet(32/46 Pages) RENESAS

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P9221-R3 Datasheet

October 20, 2017

Address and Bit

R/W

Default

Function and Description

0038HEX [1]

VRECT_OV_INT_EN

1BIN

“0” disables the INT_VRECT_OV interrupt.

"1" enables the interrupt.

0038HEX [0]

OC_Limit_Status_INT_EN

1BIN

“0” disables the INT_OC_Limit_Status interrupt.

"1" enables the interrupt.

0039HEX [7:0]

Reserved

00HEX

Table 17. Battery Charge Status

Address and Bit

R/W

Default

Function and Description

003AHEX [7:0]

Batt_Charg_status

R/W

00HEX

The application processor loads the battery charge status in

this register. This value is sent to the transmitter when bit 4 of

[a] The firmware only forwards the data from the application processor to transmitter.

Table 18. End Power Transfer

The application processor initiates the End Power Transfer (EPT).

Address and Bit

R/W

Default

Function and Description

003BHEX [7:0]

EPT_Code

R/W

00HEX

EPT_Code sent to transmitter.

Table 19. Read Register – Output Voltage

VOUT =

ADC_VOUT ∗ 6 ∗ 2.1

4095

Address and Bit

R/W

Default

Function and Description

003CHEX [7:0]

ADC_VOUT [7:0]

00HEX

8 LSB of VOUT ADC value.

003DHEX [7:4]

Reserved

0HEX

Reserved.

003DHEX [3:0]

ADC_VOUT [11:8]

0HEX

4 MSB of VOUT ADC value.

Table 20. Read Register – VRECT Voltage

VRECT =

ADC_VRECT ∗ 10 ∗ 2.1

4095

Address and Bit

R/W

Default

Function and Description

0040HEX [7:0]

ADC_VRECT [7:0]

–

8 LSB of VRECT ADC value.

0041HEX [7:4]

Reserved

0HEX

Reserved.

0041HEX [3:0]

ADC_VRECT [11:8]

–

4 MSB of VRECT ADC value.

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