105 Hardware Specifications

7

Preliminary/Subject to Change without Notice

Table 6. Input AC Timing Specifications

Vdd = 3.3

± 5% Vdc, GND = 0 Vdc

Num

Characteristic

Min

Max

Unit

Notes

10

A0–A31, PAR0–PAR7, TT0–TT4, AACK, TA, GBL, CI, WT, TV

input valid to SYSCLK (input setup)

4.0

—

ns

1

11

DL0–DL31, DH0–DH31, TBST, TSIZ0–TSIZ2. Input valid to

SYSCLK (input setup)

2.5

—

ns

2

12

HIT, TS, ARTRY, BR0, BR1, XATS input signals valid to SYSCLK

(input setup)

5.0

—

ns

3

13

Mode select inputs valid to HRST (input setup)

3 *

tSYS

—

ns

4, 5

14

LOCK, FLSHREQ, ISA_MASTER,

C/BE0–C/BE3, PAR, TRDY, IRDY, FRAME, STOP, DEVSEL,

PERR, SERR, AD0–AD31 input signals valid to SYSCLK (input

setup)

7.0

—

ns

6

15

PCI point-to-point signals input signals valid to SYSCLK (input

setup)

10.0

—

ns

7

16

SYSCLK to inputs invalid

(input hold)

1.0

—

ns

1–3,

17

SYSCLK to PCI inputs invalid

(input hold)

0.0

—

ns

6,7

18

HRST to mode select inputs invalid (input hold)

1.0

—

ns

4, 8

Notes:

All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the

1.4 V of the rising edge of SYSCLK. Processor and memory interface signals are specified from the

rising edge of the processor and memory bus clock, which is the same as SYSCLK in 1:1 mode, but

is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising

and falling edge of SYSCLK). Both input and output timings are measured at the pin.

1. Inputs are composed of the following processor interface signals—A0–A31, PAR0–PAR7,

TT0–TT4, AACK, TA, GBL, CI, WT, TV.

2. Inputs are composed of the following processor interface signals—DL0–DL31, DH0–DH31, TBST,

TSIZ0–TSIZ2.

3. Inputs are composed of the following processor and L2 interface signals—HIT, TS, ARTRY, BR0,

BR1, XATS.

4. The setup and hold time is with respect to the rising edge of HRST; see Figure 3. The following

signals encompass the mode (or configuration) pins for MPC105—RCS0, BCTL0, DL0, XATS, and

FNR.

5. tSYS is the period of the external clock (SYSCLK) in nanoseconds

6. Inputs are composed of all PCI bus signals: LOCK, FLSHREQ, ISA_MASTER, C/BE0–C/BE3,

PAR, TRDY, IRDY, FRAME, STOP, DEVSEL, PERR, SERR, AD0–AD31.

7. Inputs are composed of all PCI point-to-point signals. GNT has a setup time of 10.0 ns for a 33

MHZ PCI clock.

8. Guaranteed by design, not tested.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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