105 Hardware Specifications

11

Preliminary/Subject to Change without Notice

Figure 5 provides the JTAG clock input timing diagram.

Figure 5. Clock Input Timing Diagram

Figure 6 provides the TRST timing diagram.

Figure 6. TRST Timing Diagram

Figure 7 provides the boundary-scan timing diagram.

Figure 7. Boundary-Scan Timing Diagram

131

TCK to TDO high impedance

0

15

ns

Note:

1. Load capacitance = 20 pF

Table 8. JTAG AC Timing Specifications (Independent of SYSCLK) (Continued)

Num

Characteristic

Min

Max

Unit

TCK

2

2

1

VM

VM

VM

3

3

VM = Midpoint Voltage

4

5

TRST

TCK

6

7

INPUT DATA VALID

8

9

8

OUTPUT DATA VALID

OUTPUT DATA VALID

TCK

DATA INPUTS

DATA OUTPUTS

DATA OUTPUTS

DATA OUTPUTS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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