8

105 Hardware Specifications

Preliminary/Subject to Change without Notice

Figure 2. Input Timing Diagram

Figure 3. Mode Select Input Timing Diagram

1.3.2.3 Output AC Specifications

Table 7 provides the output AC timing specifications for the MPC105 as defined in Figure 4. These

specifications are for operation between 16.67 MHz and 33.33 MHz bus clock (SYSCLK) frequencies.

Table 7. Output AC Timing Specifications

Vdd = 3.3

± 5% Vdc, GND = 0 Vdc

Num

Characteristic

Min

Max

Unit

Notes

19

SYSCLK to output driven (output enable time)

2.0

—

ns

20

SYSCLK to output valid

(for PCI bus signals)

—

11

ns

1, 2, 3

21

SYSCLK to output valid

(for PCI point-to-point signals)

—

12

ns

1, 2, 4

22

SYSCLK to output valid (for TS, ARTRY, all non-PCI

signals except TALE, BAA, RAS/CS0–RAS/CS7, CAS/

DQM0–CAS/DQM7)

—

8.0

ns

1, 2, 7

23

SYSCLK to output valid

(for TALE, BAA)

—

10.0

ns

1, 2

24

SYSCLK to output valid

(for RAS/CS0–RAS/CS7, CAS/DQM0–CAS/DQM7)

—

9.0

ns

1, 2

14–16

VM

VM = Midpoint Voltage (1.4 V)

SYSCLK

10–12

ALL INPUTS

VM

VM = Midpoint Voltage (1.4 V)

HRST

16

MODE PINS

13

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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