MPC105ECSLASHD datasheet(10/24 Pages) NXP

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105 Hardware Specifications

Preliminary/Subject to Change without Notice

Figure 4. Output Timing Diagram

1.3.3 JTAG AC Timing Speciﬁcations

Table 8 provides the JTAG AC timing speciﬁcations.

Table 8. JTAG AC Timing Specifications (Independent of SYSCLK)

Num

Characteristic

Min

Max

Unit

TCK frequency of operation

MHz

TCK cycle time

—

TCK clock pulse width measured at 1.5 V

—

TCK rise and fall times

TRST setup time to TCK falling edge

—

TRST assert time

—

Boundary-scan input data setup time

—

Boundary-scan input data hold time

—

TCK to output data valid

TCK to output high impedance

TMS, TDI data setup time

—

TMS, TDI data hold time

—

121

TCK to TDO data valid

SYSCLK

ALL OUTPUTS

(Except TS, ARTRY)

ARTRY

VM = Midpoint Voltage (1.4 V)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

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