TMPR4955F datasheet(89/168 Pages) TOSHIBA

89 / 168 page

Chapter 6 TX4955A System Interface

6-17

6.2.8.5

Processor block write request

The master state system interface is used to issue processor block write requests.

Figure 6.2.17 illustrates a processor non-coherent block request made for 8-word data

with the “D” data pattern.

1. Processor sends a write command to the SysCmd bus, then sends a write address

to the SysAD bus.

2. Processor asserts the ValidOut* signal.

3. Processor sends data identifier to the SysCmd bus and sends data to the SysAD

bus.

4. Processor asserts the ValidOut* signal only for the number of cycles required to

transfer the data block.

5. Final data cycle directive must be included in data identifiers for the final data

cycle.

Note: There is transmission protocol of Processor block write request three kinds same as

Processor single write requests. With later G2SConfig-Regster, these modes are

selected.

Figure 6.2.17 Processor non-coherent block request protocol

6.2.8.6

External request protocol

External requests can only be issued when the system interface is in the slave state.

The external agent asserts the ExtRqst* signal, and requests use of the system

interface. The processor asserts the Release* signal, releases the system interface,

waits for it to enter the slave state, then the external agent issues an external request.

If the system interface is already in the slave mode, namely, if the processor has put

the system interface in the slave state on its own, then the external agent can

immediately issue an external request.

In the case of the external agent, the system interface must be returned to the

master state after issuing an external request. When the external agent issues a

single external request, ExtRqst* must be deasserted 2 cycles after the cycle at which

Release* is asserted. Also, when issuing a series of external requests, the ExtRqst*

signal must be asserted before the last request cycle.

Master Clock

Data5

345

Cycle

SysAD Bus

ValidOut*

Validln*

SysCmd Bus

Addr

Write

RdRdy*

WrRdy*

Release*

Master

Data0

NData

Data1

NData

Data2

NData

Data3

NData

Data4

Data6

Data7

NData

NEOD

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