TMPR4955AF datasheet(112/168 Pages) TOSHIBA

112 / 168 page

Chapter 6 TX4955A System Interface

6-40

tDS

tDO

tDH

tDO

tDH

tDS

tDO

Valid output

Valid

Input

Valid

Input

Note: These waveforms only describe edge-to-edge timing relationships.

EValid*, EReq*,

EOK*,

Int*, NMI*

PValid*

PMaster*

SysAD

SysADC

SysCmd

SysCmdP

SClock

Figure 6.3.3 System Interface Edge Timing Relationships

The Timing Summary section below describes the minimum and maximum timing

values of each signal. The sections that follow describe the timing requirements for various

bus cycles.

6.3.5

Timing Summary

In the following timing diagrams, gray-scale signals indicate values that are either

Unknown or Don’t Cares, within the specification limits. They may be any value as long

they do not violate any bus value or timing specification. The timing diagrams illustrate

cycles using the following signals:

•

PMaster

PMaster*

•

EValid

EValid*

•

PValid

PValid*

•

EOK

EOK*

•

EReq

EReq*

PMaster

PMaster*

(O)

Indicates the processor is the master of the system interface bus.

ExtAgent Cmd

ExtAgent Data

Proc Cmd

Proc Data

SysCmd

SysAD

SCycle

PMaster*

SClock

Figure 6.3.4 Sample Cycle with PMaster* Asserted, Then Deasserted

Processor drives SysAD and SysCmd buses (processor is master).

BPMaster

PMaster

PMaster is deasserted. SysAD and SysCmd buses are set to a tri-state(no bus master).

External agent drives SysAD and SysCmd buses (external agent is master).

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