TMPR4955AF datasheet(143/168 Pages) TOSHIBA

143 / 168 page

Chapter 7 JTAG Interface

7-9

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Exit 1-DR

This is a temporary controller state.

If JTMS is held low when the controller is in this state, then the controller moves

to the Pause-DR state. If JTMS is held high, the controller moves to the

Update-DR state.

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Pause-DR

This state allows the shifting of the data register selected by the instruction

When the controller is in this state, then it remains in the Pause-DR state if JTMS

is held low, or moves to the Exit2-DR state if JTMS is held high.

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Exit 2-DR

This is a temporary controller state.

When the controller is in this state, then it returns to the Shift-DR state if JTMS is

held low, or moves on to the Update-DR state if JTMS is held high.

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Update-DR

In this state, data is latched, on the falling edge of JTCK, onto the parallel outputs

of the data registers from the shift register path. The data held at the parallel

output does not change while data is shifted in the associated shift register path.

When the controller is in this state, it moves to either the Run-Test/Idle state if

JTMS is held low, or the Select-DR-Scan state if JTMS is held high.

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Capture-IR

In this state, data is parallel-loaded into the instruction register. The two least

significant bits are assigned the values “01”. The higher-order bits of the

instruction register can receive any design specific values. The Capture-IR state is

used for testing the instruction register. Faults in the instruction register, if any

exists, may be detected by shifting out the data loaded in it.

When the controller is in this state, it moves to either the Shift-IR state if JTMS is

low, or the Exit1-IR state if JTMS is high.

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Shift-IR

In this state, the instruction register is connected between JTDI and JTDO and

shifts the captured data toward its serial output on the rising edge of JTCK.

When the controller is in this state, it remains in the Shift-IR state if JTMS is low,

or moves to the Exit1-IR state if JTMS is high.

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