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S75WS256NDFBAWMB 데이터시트(PDF) 137 Page - SPANSION

부품명 S75WS256NDFBAWMB
상세설명  Stacked Multi-Chip Product (MCP)
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February 17, 2005 S75WS-N-00_00_A0
S75WS256Nxx Based MCPs
135
Data
Sheet
25.7 Erase/Program Operations
Notes:
1. Not 100% tested.
2. Asynchronous read mode allows Asynchronous program operation only. Synchronous read mode allows both
Asynchronous and Synchronous program operation.
3. In asynchronous program operation timing, addresses are latched on the falling edge of WE#. In synchronous program
operation timing, addresses are latched on the rising edge of CLK.
4. See the Erase and Programming Performance section for more information. Does not include the preprogramming time.
Parameter
Description
80 MHz 66 MHz 54 MHz Unit
JEDEC
Standard
tAVAV
tWC
Write Cycle Time (Note 1)Min
70
ns
tAVWL
tAS
Address Setup Time (Notes 2, 3)
Synchronous
Min
5
ns
Asynchronous
0
0
0
tWLAX
tAH
Address Hold Time (Notes 2, 3)
Synchronous
Min
22
3
ns
Asynchronous
0
0
0
tAVDP
AVD# Low Time
Min
8
8
8
ns
tDVWH
tDS
Data Setup Time
Min
20
20
25
ns
tWHDX
tDH
Data Hold Time
Min
0
0
0
ns
tGHWL
tGHWL
Read Recovery Time Before Write
Min
0
0
0
ns
tCAS
CE# Setup Time to AVD#
Min
0
0
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
0
0
ns
tWLWH
tWP
Write Pulse Width
Min
30
ns
tWHWL
tWPH
Write Pulse Width Highs
Min
20
20
25
ns
tSR/W
Latency Between Read and Write Operations
Min
0
0
0
ns
tVID
VACC Rise and Fall Time
Min
500
ns
tVIDS
VACC Setup Time (During Accelerated Programming)
Min
1
µs
tVCS
VCC Setup Time
Min
50
µs
tELWL
tCS
CE# Setup Time to WE#
Min
5
ns
tAVSW
AVD# Setup Time to WE#
Min
5
ns
tAVHW
AVD# Hold Time to WE#
Min
2
2
3
ns
tAVSC
AVD# Setup Time to CLK
Min
5
ns
tAVHC
AVD# Hold Time to CLK
Min
2
2
3
ns
tCSW
Clock Setup Time to WE#
Min
5
ns
tWEP
Noise Pulse Margin on WE#
Max
3
ns
tSEA
Sector Erase Accept Time-out
Max
50
µs
tESL
Erase Suspend Latency
Max
20
µs
tPSL
Program Suspend Latency
Max
20
µs
tASP
Toggle Time During Sector Protection
Typ
100
µs
tPSP
Toggle Time During Programming Within a Protected Sector
Typ
1
µs



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