S75WS256NDFBAWMB datasheet(139/216 Pages) SPANSION

139 / 216 page

February 17, 2005 S75WS-N-00_00_A0

S75WS256Nxx Based MCPs

137

Data

Sheet

Notes:

1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits.

2. In progress and complete refer to status of program operation.

3. Amax9–A14 are don’t care during command sequence unlock cycles.

4. Addresses are latched on the rising edge of CLK.

5. Either CE# or AVD# is required to go from low to high in between programming command sequences.

6. The Synchronous programming operation is dependent of the Set Device Read Mode bit in the Configuration Register.

The Configuration Register must be set to the Synchronous Read Mode.

Figure 25.11 Synchronous Program Operation Timings: CLK Latched Addresses

Note: Use setup and hold times from conventional program operation.

Figure 25.12 Accelerated Unlock Bypass Programming Timing

OE#

CE#

Data

Addresses

AVD#

WE#

CLK

VCC

555h

tWC

tWPH

tWP

tVCS

tDH

tCH

Progress

tWHWH1

Complete

Program Command Sequence (last two cycles)

Read Status Data

tDS

tAVDP

A0h

tAS

tCAS

tAH

tAVCH

tCSW

tAVSC

CE#

AVD#

WE#

Addresses

Data

OE#

ACC

Don't Care

A0h

Don't Care

VID

VIL or VIH

VID

VIDS

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