S75WS256NDFBAWMB datasheet(164/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

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Inf o rmation

strength option minimizes the noise generated on the data bus during Read operations. Normal

output drive strength should be selected when using a discrete CellularRAM device in a more

heavily loaded data bus environment. Outputs are configured at full drive strength during testing.

31.2.4

Wait Configuration (BCR[8]): Default = Wait Transitions One

Clock Before Data Valid/Invalid

The Wait configuration bit is used to determine when Wait transitions between the asserted and

the de-asserted state with respect to valid data presented on the data bus. The memory controller

will use the Wait signal to coordinate data transfer during synchronous Read and Write operations.

When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after Wait transitions

to the de-asserted or asserted state, respectively (Figure 31.3 and Figure 31.5). When A8 = 1,

the Wait signal transitions one clock period prior to the data bus going valid or invalid

(Figure 31.4).

31.2.5

Wait Polarity (BCR[10]): Default = Wait Active High

The Wait polarity bit indicates whether an asserted Wait output should be High or Low. This bit

will determine whether the Wait signal requires a pull-up or pull-down resistor to maintain the de-

asserted state.

Table 31.3 Output Impedance

BCR[5]

BCR[4]

DRIVE STRENGTH

Full

1/2

1/4

Reserved

Note: Data valid/invalid immediately after Wait transitions (BCR[8] = 0). See Figure 31.5.

Figure 31.3 Wait Configuration (BCR[8] = 0)

Note: Valid/invalid data delayed for one clock after Wait transitions (BCR[8] = 1). See Figure 31.5.

Figure 31.4 Wait Configuration (BCR[8] = 1)

Data[0]

Data[1]

High-Z

CLK

WAIT

DQ[15:0]

Data immediately valid (or invalid)

Data[0]

High-Z

CLK

WAIT

DQ[15:0]

Data valid (or invalid) after one clock delay

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