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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9033 데이터시트(PDF) 31 Page - ESS Technology,Inc |
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ES9033 데이터시트(HTML) 31 Page - ESS Technology,Inc |
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31 / 103 page  0.3.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 ES9033 Datasheet Information 31 Audio Interface Timing Audio data on DATA1-2 are sampled at the rising edges of DATA_CLK and must satisfy the setup and hold time requirements relative to the rising edge of DATA_CLK. Figure 8 - Audio interface timing Parameter Symbol Min Max Unit DATA_CLK pulse width high tDCH 9.0 ns DATA_CLK pulse width low tDCL 9.0 ns DATA_CLK cycle time tDCY 20 ns DATA_CLK duty cycle 45:55 55:45 DATAx set-up time to DATA_CLK rising edge tDS 4.1 ns DATAx hold time to DATA_CLK rising edge tDH 2.0 ns Table 9 - Audio interface timing definitions |
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