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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9033 데이터시트(PDF) 47 Page - ESS Technology,Inc |
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ES9033 데이터시트(HTML) 47 Page - ESS Technology,Inc |
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47 / 103 page  0.3.1 ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 ES9033 Datasheet Information 47 Register 1: SYS MODE CONFIG Bits [7:3] [2] [1] [0] Default 5’b00001 1’b0 1’b0 1’b1 Bits Mnemonic Description [7:3] RESERVED NA [2] ENABLE_DOP_DECODE Enables DoP decoding. • 1’b0: Disabled (default) • 1’b1: Enabled [1] ENABLE_DSD_DECODE Enables DSD decoding. • 1’b0: Disabled (default) • 1’b1: Enabled [0] ENABLE_TDM_DECODE Enables TDM decoding. • 1’b0: Disabled • 1’b1: Enabled (default) Register 2: DAC CLOCK CONFIG Bits [7] [6] [5:0] Default 1’b0 1’b0 6’d7 Bits Mnemonic Description [7] RESERVED NA [6] SELECT_IDAC_HALF Specifies whether to half CLK_IDAC divider. • 1’b0: Divide by SELECT_IDAC_NUM + 1 (default) • 1’b1: Divide by half of SELECT_IDAC_NUM + 1 Note: Can only produce half of an odd number divide [5:0] SELECT_IDAC_NUM CLK_IDAC divider. Whole number divide value + 1 for CLK_IDAC (SYS_CLK/divide_value). • 6’d0: Whole number divide value + 1 = 1 • 6’d1: Whole number divide value + 1 = 2 • 6’d63: Whole number divide value + 1 = 64 |
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