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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ES9033 데이터시트(PDF) 32 Page - ESS Technology,Inc |
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ES9033 데이터시트(HTML) 32 Page - ESS Technology,Inc |
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32 / 103 page  a 0.3.1 ES9033 Datasheet Information ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 32 Analog Features APLL Figure 9 - Functional Block Diagram of ES9033 APLL The ES9033 has a built in Analog PLL (APLL) for generating frequencies that are unavailable externally. For calculation of the PLL frequency output, use the following formula: ������������������������=( ������������������ ������������ )∗ ������������������ ������������ ������������������ = (225) ������������������������������ Where: a. FBDIV is a 24-bit number b. Fvco = Fout * NO, where Fvco must be between 90MHz and 100MHz c. NI = input dividing ratio, • Accessible from Reg 202-200[9:1], PLL_CLK_IN_DIV d. NO = output dividing ratio • Accessible from Reg 202-200[13:10], PLL_CLK_OUT_DIV e. NFB = feedback dividing ratio, • Accessible from Reg 199-197[23:0], PLL_CLK_FB_DIV PLL Registers • NI – Register 200-202[9:1] PLL_CLK_IN_DIV • NO – Register 200-202[13:10] PLL_CLK_OUT_DIV • FBDIV – Register 197-199[23:0] PLL_CLK_FB_DIV GPIO1/MCLK DATA_CLK φ REG 1V8 NFB NO NI REG 1V2 FOUT |
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