AD4080BBCZ datasheet(47/95 Pages) AD

47 / 95 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. 0 | 47 of 95

Figure 77. Single Lane LVDS, Echo Clock Mode, LVDS_CNV_CLK_CNT Position Example

Figure 78. Dual Lane LVDS, Echo Clock Mode, LVDS_CNV_CLK_CNT Position Example

Table 20. Valid LVDS_CNV_CLK_CNT Settings

LVDS_CNV_CLK_CNT

Settings

Clock Count Number

Single Lane Mode

Dual Lane Mode

0b0000

0b0001

0b0010

0b0011

0b0100

0b0101

Selection not valid

0b0110

Selection not valid

0b0111

Selection not valid

0b1000

Selection not valid

0b1001

Selection not valid

As a overview guide, Table 21 indicates the minimum required

LVDS_CNV_CLK_CNT settings for various conversion rates.

The maximum tMSB of 22.4 ns, that is with the gain error correction

enabled (see the Gain Error Correction section), is used for all

calculations in Table 21. On power-up, the value of the gain error

correction is 0x200, disabling the correction and allowing for a lower

latency result. In this case, tMSB is 18 ns and a latency of 46.25 ns

can be achieved.

Using this example, the same formula is used, again taking a single

lane 40 MSPS example, the LVDS clock runs at 400 MHz and

yields (18 ns/2.5 ns) + 1.5, resulting in an LVDS_CNV_CLK_CNT of

8 and a total result latency of (8 + 0.5) × 2.5 ns + tCYC = 46.25 ns

latency.

To aid alignment of this valid result data position with the digital host

of the user, the ADC Data Interface Configuration A register (see

the ADC Data Interface Configuration A Register section, Address

0x15) contains access to the interface check feature enabled by

setting the INTF_CHK_EN bit. When this bit is set, the ADC results

are no longer output on the interface, and the output is replaced

with a fixed pattern 20b1010 1100 0101 1101 0110 (0xA C5D6).

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