AD4080BBCZ datasheet(10/95 Pages) AD

10 / 95 page

Data Sheet

AD4080

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

analog.com

Rev. 0 | 10 of 95

Table 6. Pin Function Descriptions (Continued)

Pin No.

Mnemonic

Type1

Description

In SPI data interface mode, this pin functions as a chip select input (data interface chip

select).

B1, B2, C1, C2, F5,

F6, G5

REFGND

Reference Grounds. Connect any external reference decoupling capacitors across

REFIN and REFGND. REFGND must be tied with a low impedance path to GND.

VDDLDO

LDO Supply Rail Input.

This supply rail is internally decoupled by a 220 nF capacitor to GND. The two internal,

1.1 V, LDO voltage regulators can be supplied from a source connected to this input

in the 1.5 V to 2.7 V range. If this pin is left open, the internal regulators automatically

power off and both VDD11and IOVDD must be connected with an external voltage

source within their allowed specification limits.

If VDDLDO is connected to a voltage source, neither VDD11 nor IOVDD should be

connected to any external voltage source.

B4, B5

DCO−, DCO+

LVDS Echo Clock Outputs.

In LVDS data interface mode (default), this pin pair outputs a buffered and delayed

version of CLK+ and CLK−. Data outputs from LVDS Data Lane DA+ and Data Lane

DA− (and Data Lane DB+ and Data Lane DB− if active) are clocked out in alignment

with both rising and falling edges of DCO+ and DCO−. In SPI data interface mode (or

if the echo clock mode is disabled while in LVDS data interface mode), these pins can

be left unconnected.

IOGND

Digital Interface Supply Ground Reference. This pin must be connected to the same

ground plane as all other GND pins.

All pins specified as type DI, DO, or DI/O must use this ground reference.

CLK+/DCLK

Data Interface Clock Input Multifunction Pin.

In LVDS data interface mode (default), this pin serves as half of the differential data

clock input, and an external 100 Ω termination resistor must be present between it and

the CLK− pin.

In SPI data interface mode, the single-ended data clock signal must be applied to this

pin.

C3 to C5, D3 to D5,

E3 to E5

GND

Grounds. All ground pins must be connected to a PCB GND plane.

DB+/SDOC

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB− serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output C (SDOC), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

falling edge of the data interface clock (DCLK).

This pin must left unconnected if not being used.

DA+/SDOA

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DA− serves as the

primary LVDS Data Lane A.

In SPI data interface mode, this pin functions as Serial Data Output A (SDOA), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

falling edge of the data interface clock (DCLK).

This pin must left unconnected if not being used.

IN+

Positive Analog Differential Input.

AUXIN+

Positive Auxiliary Analog Differential Input.

DB−/SDOD

Data Interface Output Multifunction Pin.

In LVDS data interface mode (default), this output pin along with DB+ serves as the

optional, secondary LVDS Data Lane B. If unused, leave unconnected.

In SPI data interface mode, this pin functions as Serial Data Output D (SDOD), which

is active in a four-lane configuration only. Result data is shifted out of this pin on the

AD4080BBCZ 데이터시트(PDF) 10 Page - Analog Devices

AD4080BBCZ 데이터시트(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95

데이터시트 다운로드

링크 URL