AD4080BBCZ datasheet(53/95 Pages) AD

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Data Sheet

AD4080

DIGITAL FEATURES

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Rev. 0 | 53 of 95

OVERVIEW

The AD4080 includes several useful digital features that offer great

solution benefits to many applications. These features can be

individually enabled by the user, when required. A brief overview

follows for these features, in depth explanation and definition of

these features are found in the following sections.

►

Event Detection: This feature allows the detection when the

analog input has crossed user-configured thresholds. Such de-

tections can be flagged in the configuration registers, output to a

GPIO, or used to trigger the result FIFO.

►

Result FIFO: This feature allows the acquisition of records of

up to 16,384 conversion results into the on-chip memory. These

acquisitions can be read back to the host controller via LVDS

or the SPI data interface. The results stored in the FIFO can

be either unprocessed ADC results or those that have been

processed through the digital filter feature.

►

Digital Filter: This feature offers three different digital filter config-

urations, each with a wide range of decimation rates, allowing

oversampling benefits and the close control of the signal band-

width.

►

System Error Correction Coefficients: Although the AD4080 of-

fers excellent factory calibrated precision with minimal offset and

gain errors, this feature allows the user to correct for signal chain

that may be present within their application.

EVENT DETECTION

The AD4080 includes an event detection feature, whereby the user

can either indicate when a particular analog input threshold level

is crossed or monitor a GPIO configured as an input. An internally

generated event can then be used to set a flag in the configuration

memory or routed to a configured GPIO output to be used to alert

a host controller that a threshold condition is breached. It is also

possible for a user to route an external signal to the AD4080 to be

used as an external trigger. An internally or externally generated

event can also be used to trigger the integrated result FIFO (see

the Result FIFO section). The mechanism for this is explained

in the Event Detection for FIFO section. The threshold detection

compares a converted voltage code to a user-configured code

because this is done in a sample by sample basis, and events

immediately trigger, level hysteresis setting is also configurable to

prevent unwanted triggering.

Figure 80. Internally Generated Event Detection Signal Path

The Figure 80 serves as an aid with detailing the configuration and

operation of the event detection of the AD4080.

Table 26. Event Detection

INT_EVENT_EN Bit

(Address 0x1C)

Mode

Trigger Source

Comment

External event

GPIO_x_SEL = 4b1001, that is, configured for

EXT_EVENT

Event triggers when a logic high is detected on the

selected GPIO input.

Internal event

ADC Results threshold detection is enabled.

HI_THRESHOLD (Address 0x21 and Address 0x22) and

LO_THRESHOLD (Address 0x23 and Address 0x24) set

the upper and lower ADC result (or the digital filter result)

code threshold for the event to be triggered.

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