 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
AD4080BBCZ 데이터시트(PDF) 67 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD4080BBCZ 데이터시트(HTML) 67 Page - Analog Devices |
|
|
67 / 95 page  Data Sheet AD4080 DIGITAL FEATURES analog.com Rev. 0 | 67 of 95 Filter Reset Conditions Direct LVDS When accessing the filtered data directly via the LVDS interface, the AD4080 resets the filter by the following two methods: ► By configuring the filter, by issuing a write to the filter configu- ration register, Bits[7:0] (see the Filter Configuration Register section, Address 0x29). ► By asserting a GPIO that’ is configured for FILTER_SYNC opera- tion. With FIFO When the FIFO is enabled, the user must use a GPIO configured as FILTER_SYNC to reset the filter for each FIFO acquisition. Filter Synchronization Set GPIO_x_SEL to FILTER_SYNC to configure this input providing synchronization to the controller of the user, which can be used to synchronize the filters across multiple AD4080 devices. The FILTER_SYNC signal is an active low input, and this signal must be held low for a minimum of one conversion cycle to reset and synchronize the digital filter. Refer to Figure 96 for the timing requirements for a filter reset. Figure 96. Filter Reset Timing |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
