MC68HC908GR4MP datasheet(213/286 Pages) FREESCALE

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Queuing Transmission Data

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

213

20.6 Queuing Transmission Data

The double-buffered transmit data register allows a data byte to be queued and transmitted. For an SPI

configured as a master, a queued data byte is transmitted immediately after the previous transmission

has completed. The SPI transmitter empty flag (SPTE) indicates when the transmit data buffer is ready

to accept new data. Write to the transmit data register only when the SPTE bit is high. Figure 20-8 shows

the timing associated with doing back-to-back transmissions with the SPI (SPSCK has CPHA: CPOL =

1:0).

Figure 20-8. SPRF/SPTE CPU Interrupt Timing

The transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes

between transmissions as in a system with a single data buffer. Also, if no new data is written to the data

buffer, the last value contained in the shift register is the next data word to be transmitted.

For an idle master or idle slave that has no data loaded into its transmit buffer, the SPTE is set again no

more than two bus cycles after the transmit buffer empties into the shift register. This allows the user to

queue up a 16-bit value to send. For an already active slave, the load of the shift register cannot occur

until the transmission is completed. This implies that a back-to-back write to the transmit data register is

not possible. The SPTE indicates when the next write can occur.

BIT

MOSI

SPSCK

SPTE

WRITE TO SPDR

CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2

CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.

BYTE 1 TRANSFERS FROM TRANSMIT DATA

SPRF

READ SPSCR

MSB BIT

BIT

LSB MSB BIT

BIT

LSB MSB BIT

BYTE 2 TRANSFERS FROM TRANSMIT DATA

CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE

BYTE 3 TRANSFERS FROM TRANSMIT DATA

FIRST INCOMING BYTE TRANSFERS FROM SHIFT

CPU READS SPSCR WITH SPRF BIT SET.

SECOND INCOMING BYTE TRANSFERS FROM SHIFT

AND CLEARING SPTE BIT.

SPRF BIT.

3 AND CLEARING SPTE BIT.

SPRF BIT.

12 CPU READS SPDR, CLEARING SPRF BIT.

BIT

BYTE 1

BYTE 2

BYTE 3

READ SPDR

CPU READS SPDR, CLEARING SPRF BIT.

11 CPU READS SPSCR WITH SPRF BIT SET.

CPHA:CPOL = 1:0

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