MC68HC908GR4MP datasheet(90/286 Pages) FREESCALE

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Configuration Register (CONFIG)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

OSCSTOPENB— Oscillator Stop Mode Enable Bar Bit

OSCSTOPENB enables the oscillator to continue operating during stop mode. Setting the

OSCSTOPENB bit allows the oscillator to operate continuously even during stop mode. This is useful

for driving the timebase module to allow it to generate periodic wakeup while in stop mode. (See Clock

Generator Module (CGM) subsection Stop Mode.)

1 = Oscillator enabled to operate during stop mode

0 = Oscillator disabled during stop mode (default)

SCIBDSRC — SCI Baud Rate Clock Source Bit

SCIBDSRC controls the clock source used for the SCI. The setting of this bit affects the frequency at

which the SCI operates.

1 = Internal data bus clock used as clock source for SCI

0 = External oscillator used as clock source for SCI

COPRS — COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. See Chapter 9 Computer Operating

Properly (COP).

1 = COP timeout period = 8176 CGMXCLK cycles

0 = COP timeout period = 262,128 CGMXCLK cycles

LVISTOP — LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.

Reset clears LVISTOP. See Stop Mode.

1 = LVI enabled during stop mode

0 = LVI disabled during stop mode

LVIRSTD — LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).

1 = LVI module resets disabled

0 = LVI module resets enabled

LVIPWRD — LVI Power Disable Bit

LVIPWRD disables the LVI module. See Chapter 14 Low-Voltage Inhibit (LVI).

1 = LVI module power disabled

0 = LVI module power enabled

LVI5OR3 — LVI 5V or 3V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module. See Chapter 14 Low-Voltage Inhibit

(LVI). The voltage mode selected for the LVI should match the operating VDD. See Chapter 23

Electrical Specifications for the LVI’s voltage trip points for each of the modes.

1 = LVI operates in 5V mode.

0 = LVI operates in 3V mode.

SSREC — Short Stop Recovery Bit

Address:

$001F

Bit 7

654321

Bit 0

Read:

COPRS

LVISTOP

LVIRSTD

LVIPWRD

LVI5OR3

SSREC

STOP

COPD

Write:

Reset:

0000

See Note

000

Note: LVI5OR3 bit is only reset via POR (power-on reset)

Figure 8-2. Configuration Register 1 (CONFIG1)

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