MC68HC908GR4MP datasheet(84/286 Pages) FREESCALE

84 / 286 page

Clock Generator Module (CGMC)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

7.5.5 PLL VCO Range Select Register

NOTE

PMRS may be called PVRS on other HC08 derivatives.

The PLL VCO range select register (PMRS) contains the programming information required for the

hardware configuration of the VCO.

VRS7–VRS0 — VCO Range Select Bits

These read/write bits control the hardware center-of-range linear multiplier L which, in conjunction with

E (see 7.3.3 PLL Circuits, 7.3.6 Programming the PLL, and 7.5.1 PLL Control Register), controls the

hardware center-of-range frequency, fVRS. VRS7–VRS0 cannot be written when the PLLON bit in the

PCTL is set. (See 7.3.7 Special Programming Exceptions.) A value of $00 in the VCO range select

Clock Selector Circuit and 7.3.7 Special Programming Exceptions.). Reset initializes the register to $40

for a default range multiply value of 64.

NOTE

The VCO range select bits have built-in protection such that they cannot be

written when the PLL is on (PLLON = 1) and such that the VCO clock

cannot be selected as the source of the base clock (BCS = 1) if the VCO

range select bits are all clear.

The PLL VCO range select register must be programmed correctly.

Incorrect programming can result in failure of the PLL to achieve lock.

7.5.6 PLL Reference Divider Select Register

NOTE

PMDS may be called PRDS on other HC08 derivatives.

The PLL reference divider select register (PMDS) contains the programming information for the modulo

reference divider.

Address:

$003A

Bit 7

654321

Bit 0

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

01000000

Figure 7-8. PLL VCO Range Select Register (PMRS)

Address:

$003B

Bit 7

654321

Bit 0

Read:

0000

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

00000001

= Unimplemented

Figure 7-9. PLL Reference Divider Select Register (PMDS)

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