MC68HC908GR4MP datasheet(63/286 Pages) FREESCALE

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MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

Chapter 6

Break Module (BRK)

6.1 Introduction

This section describes the break module. The break module can generate a break interrupt that stops

normal program flow at a defined address to enter a background program.

6.2 Features

Features of the break module include:

•

Accessible input/output (I/O) registers during the break interrupt

•

CPU-generated break interrupts

•

Software-generated break interrupts

•

COP disabling during break interrupts

6.3 Functional Description

When the internal address bus matches the value written in the break address registers, the break module

issues a breakpoint signal to the SIM. The SIM then causes the CPU to load the instruction register with

a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and

$FEFD in monitor mode).

The following events can cause a break interrupt to occur:

•

A CPU-generated address (the address in the program counter) matches the contents of the break

address registers.

•

Software writes a logic 1 to the BRKA bit in the break status and control register.

When a CPU-generated address matches the contents of the break address registers, the break interrupt

is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and

returns the MCU to normal operation. Figure 6-1 shows the structure of the break module.

6.3.1 Flag Protection During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear status bits during

the break state.

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