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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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MC68HC908GR4MP 데이터시트(PDF) 102 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP 데이터시트(HTML) 102 Page - Freescale Semiconductor, Inc |
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102 / 286 page  Central Processing Unit (CPU) MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 102 Freescale Semiconductor A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. 10.6 Instruction Set Summary Table 10-1 provides a summary of the M68HC08 instruction set. Table 10-1. Instruction Set Summary (Sheet 1 of 6) Source Form Operation Description Effect on CCR VH I N Z C ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP Add with Carry A ← (A) + (M) + (C) – IMM DIR EXT IX2 IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP Add without Carry A ← (A) + (M) – IMM DIR EXT IX2 IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 AIS #opr Add Immediate Value (Signed) to SP SP ← (SP) + (16 « M) –––– –– IMM A7 ii 2 AIX #opr Add Immediate Value (Signed) to H:X H:X ← (H:X) + (16 « M) –––– –– IMM AF ii 2 AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP Logical AND A ← (A) & (M) 0 – – – IMM DIR EXT IX2 IX1 IX SP1 SP2 A4 B4 C4 D4 E4 F4 9EE4 9ED4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP Arithmetic Shift Left (Same as LSL) –– DIR INH INH IX1 IX SP1 38 48 58 68 78 9E68 dd ff ff 4 1 1 4 3 5 ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP Arithmetic Shift Right –– DIR INH INH IX1 IX SP1 37 47 57 67 77 9E67 dd ff ff 4 1 1 4 3 5 BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 –––– –– REL 24 rr 3 BCLR n, opr Clear Bit n in M Mn ← 0 –––– –– DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 –––– –– REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 –––– –– REL 27 rr 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC ← (PC) + 2 + rel ? (N ⊕ V) = 0 –––– –– REL 90 rr 3 BGT opr Branch if Greater Than (Signed Operands) PC ← (PC) + 2 + rel ? (Z) | (N ⊕ V) = 0 –––– –– REL 92 rr 3 C b0 b7 0 b0 b7 C |
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