MC68HC908GR4MP datasheet(129/286 Pages) FREESCALE

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LVI Status Register

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

129

14.3.4 LVI Trip Selection

The LVI5OR3 bit in the configuration register selects whether the LVI is configured for 5V or 3V protection.

NOTE

The microcontroller is guaranteed to operate at a minimum supply voltage.

The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than this. (See

Chapter 23 Electrical Specifications for the actual trip point voltages.)

14.4 LVI Status Register

The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level.

LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage. See

Table 14-1. Reset clears the LVIOUT bit.

14.5 LVI Interrupts

The LVI module does not generate interrupt requests.

14.6 Low-Power Modes

The STOP and WAIT instructions put the MCU in low power-consumption standby modes.

14.6.1 Wait Mode

If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can

generate a reset and bring the MCU out of wait mode.

14.6.2 Stop Mode

If enabled in stop mode (LVISTOP bit in the configuration register is set), the LVI module remains active

in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out

of stop mode.

Address:

$FE0C

Bit 7

654321

Bit 0

Read:

LVIOUT

0000000

Write:

Reset:

00000000

= Unimplemented

Figure 14-3. LVI Status Register (LVISR)

Table 14-1. LVIOUT Bit Indication

VDD

LVIOUT

VDD > VTRIPR

VDD < VTRIPF

VTRIPF < VDD < VTRIPR

Previous value

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