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MC68HC908GR4MP 데이터시트(PDF) 187 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP 데이터시트(HTML) 187 Page - Freescale Semiconductor, Inc |
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187 / 286 page ![]() MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 187 Chapter 19 System Integration Module (SIM) 19.1 Introduction This section describes the system integration module (SIM). Together with the CPU, the SIM controls all MCU activities. A block diagram of the SIM is shown in Figure 19-1. Table 19-1 is a summary of the SIM input/output (I/O) registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: • Bus clock generation and control for CPU and peripherals: – Stop/wait/reset/break entry and recovery – Internal clock control • Master reset control, including power-on reset (POR) and COP timeout • Interrupt arbitration: Table 19-1 shows the internal signal names used in this section. Table 19-1. Signal Name Conventions Signal Name Description CGMXCLK Buffered version of OSC1 from clock generator module (CGM) CGMVCLK PLL output CGMOUT PLL-based or OSC1-based clock output from CGM module (Bus clock = CGMOUT divided by two) IAB Internal address bus IDB Internal data bus PORRST Signal from the power-on reset module to the SIM IRST Internal reset signal R/W Read/write signal |
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