SMC032BFY6 datasheet(52/91 Pages) STMICROELECTRONICS

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CF-ATA registers

SMCxxxBF

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9.9

Status & Alternate Status Registers

The Status & Alternate Status registers are located at addresses 1F7h [177h] and 3F6h

[376h], respectively. Offsets are 7h and Eh.

These registers return the Card status when read by the host.

Reading the Status Register clears a pending interrupt. Reading the Auxiliary Status

The Status Register should be accessed in Byte mode; in Word mode it is recommended

that Alternate Status Register is used. The status bits are described as follows

9.9.1

Bit 7 (BUSY)

The busy bit is set when only the Card can access the command register and buffer, The

host is denied access. No other bits in this register are valid when this bit is set to ‘1’.

9.9.2

Bit 6 (RDY)

This bit indicates whether the device is capable of performing CompactFlash Memory Card

operations. This bit is cleared at power up and remains cleared until the Card is ready to

accept a command.

9.9.3

Bit 5 (DWF)

When set this bit indicates a Write Fault has occurred.

9.9.4

Bit 4 (DSC)

This bit is set when the Card is ready.

9.9.5

Bit 3 (DRQ)

The Data Request is set when the Card requires information be transferred either to or from

the host through the Data register. The bit is cleared by the next command.

9.9.6

Bit 2 (CORR)

This bit is set when a Correctable data error has been encountered and the data has been

corrected. This condition does not terminate a multi-sector read operation.

9.9.7

Bit 1 (IDX)

This bit is always set to ‘0’.

Table 44.

Drive/Head Register

LBA

DRV

HS3

HS2

HS1

HS0

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