SMC032BFY6 datasheet(32/91 Pages) STMICROELECTRONICS

32 / 91 page

Command Interface

SMCxxxBF

32/91

Figure 9.

True IDE Multi-Word DMA Mode Read/Write waveforms

−CS0, −CS1

−IORD/−IOWR

Read Data D0-D15

Write Data D0-D15

ai13117

VALID

−∆ΜΑΡΘ

−∆ΜΑΧΚ

VALID

tLW, tLR

tKW

tKR

Table 23.

True IDE Multi-Word DMA Mode Read/Write timing

Symbol

Parameter

Mode 0

Mode 1

Mode 2

Mode 3

Mode 4

Unit

(1)

Cycle time (min)

480

150

120

100

(1)

-IORD / -IOWR asserted width (min)

215

-IORD data access (max)

150

-IORD data hold (min)

-IORD/-IOWR data setup (min)

100

-IOWR data hold (min)

DMACK to –IORD/-IOWR setup (min)

-IORD / -IOWR to -DMACK hold (min)

tKR

(1)

-IORD Low width (min)

tKW

(1)

-IOWR Low width (min)

215

tLR

-IORD to DMARQ delay (max)

120

tLW

-IOWR to DMARQ delay (max)

CS(1:0) valid to –IORD / -IOWR

CS(1:0) hold

10101010

-DMACK

t0 is the minimum total cycle time. tD is the minimum command active time. tKR and tKW are the minimum command

recovery time or command inactive time for input and output cycles, respectively. The actual cycle time is the sum of the

actual command active time and the actual command inactive time. The timing requirements of t0, tD, tKR, and tKW must be

respected. t0 is higher than tD + tKR or tD + tKW, for input and output cycles respectively. This means the host can lengthen

either tD or tKR/tKW, or both, to ensure that t0 is equal to or higher than the value reported in the device’s identify device

data. A CompactFlash Storage Card implementation shall support any legal host implementation.

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