SMC032BFY6 datasheet(38/91 Pages) STMICROELECTRONICS

38 / 91 page

Card Configuration

SMCxxxBF

38/91

6.5

Attribute Memory Function

Attribute memory is a space where identification and configuration information are stored.

Only 8 bit wide accesses at even addresses can be performed in this area. The Card

configuration registers are also located in the Attribute Memory area, at base address 200h.

Attribute memory is not accessible in True IDE mode of operation.

For the Attribute Memory Read function, signals –REG and –OE must be active and –WE

inactive during the cycle. As in the Main Memory Read functions, the signals –CE1 and –

CE2 control the even and odd Byte address, but only the even Byte data is valid during the

Attribute Memory access. Refer to Table 32 for signal states and bus validity.

Table 32.

Attribute Memory Function

Function Mode

–REG

–CE2

(1)

–CE1

(1)

A10

–OE

(1)

–WE

(1)

D15 to D8

D7 to D0

Standby

XXXXX

High-Z

Read Byte Access CIS

(8 bits)

LLLL

High-Z

Even Byte

Write Byte Access CIS

(8 bits) Invalid

Don’t Care Even Byte

Read Byte Access

Configuration

(8 bits)

High-Z

Even Byte

Write Byte Access

Configuration

(8 bits)

Don’t Care Even Byte

Read Word Access CIS

(16 bits)

Not Valid

Even Byte

Write Word Access CIS

(16 bits) Invalid

Don’t Care Even Byte

Read Word Access

Configuration (16 bits)

Not Valid

Even Byte

Write Word Access

Configuration (16 bits)

Don’t Care Even Byte

The –CE signal or both the –OE signal and the –WE signal must be de-asserted between consecutive cycle operations.

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