SMC032BFY6 datasheet(30/91 Pages) STMICROELECTRONICS

30 / 91 page

Command Interface

SMCxxxBF

30/91

5.4

True IDE mode

The timing waveforms for True IDE mode and True IDE DMA mode of operation in this

section are drawn using the conventions in the ATA-4 specification, which are different than

the conventions used in the PCMCIA specification and earlier versions of this specification.

Signals are shown with their asserted state as High regardless of whether the signal is

actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16

signals are shown in the waveforms inverted from their electrical states on the bus.

Figure 8.

True IDE PIO mode Read/Write waveforms

The device addresses consists of

−CS0, −CS1, and A2-A0.

The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit).

−IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.

thCE(IOWR)

tIWHEH

CE Hold following IOWR

tsuREG(IOWR) tRGLIWL

REG Setup before IOWR

thREG(IOWR)

tIWHRGH REG Hold following IOWR

tdfIOIS16(A)

tAVISL

IOIS16 Delay Falling from

Address

(2)

tdrIOIS16(A)

tAVISH

IOIS16 Delay Rising from

Address

(2)

ST CF does not assert the WAIT signal.

-IOIS16 is not supported in this mode.

Table 21.

I/O Write timing(1) (continued)

Cycle Time Mode

250ns

120ns

100ns

80ns

Unit

Symbol

IEEE

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

A0-A2,

−CS0, −CS1(1)

ADDRESS VALID

−IORD/−IOWR

Write Data D0-D15(2)

Read Data D0-D15(2)

−IOCS16(3)

ai10086b

t2i

t6z

VALID

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