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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PM8621 데이터시트(PDF) 69 Page - PMC-Sierra, Inc |
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PM8621 데이터시트(HTML) 69 Page - PMC-Sierra, Inc |
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69 / 184 page  NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 68 Document ID: PMC-2010850, Issue 1 Register 009H: NSE-8G Master Clock Monitor Bit Type Function Default Bit 31:2 R Unused X Bit 1 R RC1FPA X Bit 0 R SYSCLKA X When a monitored clock signal makes a low to high transition, the corresponding register bit is set high. The bit will remain high until this register is read, at which point all the bits in this register are cleared. A lack of transitions is indicated by the corresponding register bit reading low. This register should be read at periodic intervals to detect clock failures. SYSCLKA The SYSCLK active bit (SYSCLKA) detects low to high transitions on the SYSCLK input. SYSCLKA is set high on a rising edge of SYSCLK, and is set low when this register is read. RC1FPA The RC1FP active bit (RC1FPA) detects low to high transitions on the RC1FP input. RC1FPA is set high on a rising edge of RC1FP, and is set low when this register is read. |
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