PM8621 datasheet(72/184 Pages) PMC

72 / 184 page

NSE-8G™ Standard Product Data Sheet

Preliminary

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

Document ID: PMC-2010850, Issue 1

Bit

Type

Function

Default

Bit 31:6

Unused

Bit 5

R/W

TOPINTE

Bit 4

R/W

CSUINTE

Bit 3

R/W

R8TDINTE

Bit 2

R/W

T8TEINTE

Bit 1

R/W

ILCINTE

Bit 0

R/W

DCBINTE

This register allows the CPU to disable or enable NSE-8G Subsystem interrupts with a single

write.

TOPINTE

This bit, when ‘1’, enables the generation of interrupts from the Top_level i.e.

R8C1EXTRAINT and R8C1MISSINT interrupts. When set to ‘0’ R8C1EXTRAINT and

R8C1MISSINT interrupts are disabled .

CSUINTE

This bit, when ‘1’, enables the generation of interrupts from CSU1 control. When set to ‘0’

CSU1 control interrupts are disabled .

R8TDINTE

This bit, when ‘1’, enables the generation of interrupts from R8TD blocks. When set to ‘0’ all

R8TD interrupts are disabled .

T8TEINTE

This bit, when ‘1’, enables the generation of interrupts from T8TE blocks. When set to ‘0’ all

T8TE interrupts are disabled .

ILCINTE

This bit, when ‘1’, enables the generation of interrupts from ILC blocks. When set to ‘0’ all

ILC interrupts are disabled .

DCBINTE

This bit, when ‘1’, enables the generation of interrupts from the DCB block. When set to ‘0’

DCB interrupts are disabled .

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