PPC440GP-3CC466C datasheet(14/83 Pages) AMCC

14 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

IIC Bus Interface

Features include:

• Two IIC interfaces provided

• Support for Philips® Semiconductors I2C Specification, dated 1995

• Operation at 100kHz or 400kHz

•8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed VDD IIC interface

• Two independent 4 x 1 byte data buffers

• Twelve memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Provides full management of all IIC bus protocols

• Programmable error recovery

General Purpose Timers (GPT)

Provides a separate time base counter and additional system timers in addition to those defined in the processor

core.

• 32-bit Time Base Counter driven by the OPB bus clock

• Five 32-bit compare timers

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master

accesses.

• 31 of the 32 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose.

• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero,

tri-stated if output bit is 1).

PPC440GP-3CC466C 데이터시트(PDF) 14 Page - Applied Micro Circuits Corporation