PPC440GP-3CC466C datasheet(73/83 Pages) AMCC

73 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

I/O Timing—DDR SDRAM TDS

Notes:

1. All of the DQS signals are referenced to MemClkOut0(0).

2. The TDS values in the table include 3/4 of a cycle at the indicated clock speed.

3. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle

time for the lower clock frequency (TDS - 5.625 + 0.75TCYC).

Clock Speed (MHz)

Signal Name

TDS (ns)

Minimum

Maximum

133

DQS0

6.25

133

DQS1

6.25

133

DQS2

6.25

133

DQS3

6.25

133

DQS4

6.25

133

DQS5

6.25

133

DQS6

6.25

133

DQS7

6.25

133

DQS8

6.25

I/O Timing—DDR SDRAM TSK, TSA, and THA

Notes:

1. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).

2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and

subtract TSK maximum (0.75TCYC - TSKmax).

3. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add

TSK minimum (0.25TCYC + TSKmin).

Clock Speed (MHz)

Signal Name

TSK (ns)

TSA (ns)

THA (ns)

Minimum

Maximum

Minimum

133

MemAddr00:12

0.4

1.2

4.425

2.275

133

BA0:1

0.4

1.2

4.425

2.275

133

BankSel0:3

0.4

1.2

4.425

2.275

133

ClkEn0:3

0.4

1.2

4.425

2.275

133

CAS

0.4

1.2

4.425

2.275

133

RAS

0.4

1.2

4.425

2.275

133

0.4

1.2

4.425

2.275

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