PPC440GP-3CC466C datasheet(6/83 Pages) AMCC

6 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

PPC440GP Functional Block Diagram

The PPC440GP is designed using the IBM® Microelectronics Blue Logic™ methodology in which major functional

blocks are integrated together to create an application-specific product (ASIC). This approach provides a

consistent way to create complex ASICs using IBM CoreConnect Bus™ Architecture.

Note: IBM CoreConnect buses provide:

• 128-bit PLB interfaces up to 133.33MHz

• 32-bit OPB interfaces up to 66.66MHz, 266MB/s

Address Maps

The PPC440GP incorporates two address maps. The first is a fixed processor system memory address map. This

address map defines the possible contents of various address regions which the processor can access. The

second address map is for Device Configuration Registers (DCRs). The DCRs are accessed by software running

on the PPC440GP processor through the use of mtdcr and mfdcr instructions.

Processor Core

DCR Bus

32KB

On-chip Peripheral Bus (OPB)

GPIO

IIC

UART

DMA

Bridge

Processor Local Bus (PLB)

DDR SDRAM

External

Bus

Controller

Clock

Control

Reset

Power

Mgmt

JTAG

Trace

Timers

MMU

Controller

OPB

Interrupt

Controller

Arb

32-bit addr

32-bit data

13-bit addr

32/64-bit data

External

Bus Master

Controller

Universal

I-Cache

32KB

D-Cache

(4-Channel)

133MHz max

66MHz max

SRAM

8KB

PPC440

45 internal

13 external

PCI-X

Bridge

MAL

Ethernet

133MHz max

DCRs

1 MII

2 RMII

Timers

PPC440GP-3CC466C 데이터시트(PDF) 6 Page - Applied Micro Circuits Corporation

PPC440GP-3CC466C 데이터시트(HTML) 6 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

데이터시트 다운로드

링크 URL