MNSC140CORE datasheet(40/88 Pages) FREESCALE

40 / 88 page

MSC8122 Technical Data, Rev. 13

2-6

Freescale Semiconductor

Specifications

2.5.3

Clock and Timing Signals

The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum

frequency values for internal (Core, Reference, Bus, and DSI) and external (CLKIN and CLKOUT) clocks. The user

must ensure that maximum frequency values are not exceeded.

Figure 2-3.

Start-Up Sequence with VDD Raised Before VDDH with CLKIN Started with VDDH

Table 2-6.

Maximum Frequencies

Characteristic

Maximum in MHz

Core frequency

300/400/500

Reference frequency (REFCLK)

100/133/166

Internal bus frequency (BLCK)

100/133/166

DSI clock frequency (HCLKIN)

•

Core frequency = 300 MHz

•

Core frequency = 400/500 MHz

HCLKIN

≤ (min{70 MHz, CLKOUT})

HCLKIN

≤ (min{100 MHz, CLKOUT})

External clock frequency (CLKIN or CLKOUT)

100/133/166

Table 2-7.

Clock Frequencies

Characteristics

Symbol

300 MHz Device

400 MHz Device

500 MHz Device

Min

Max

Min

Max

Min

Max

CLKIN frequency

FCLKIN

100

133.3

166.7

BCLK frequency

FBCLK

100

133.3

166.7

Reference clock (REFCLK) frequency

FREFCLK

100

133.3

166.7

Output clock (CLKOUT) frequency

FCLKOUT

100

133.3

166.7

SC140 core clock frequency

FCORE

200

300

200

400

200

500

Note:

The rise and fall time of external clocks should be 3 ns maximum

Table 2-8.

System Clock Parameters

Characteristic

Min

Max

Unit

Phase jitter between BCLK and CLKIN

—

0.3

CLKIN frequency

see Table 2-7

MHz

CLKIN slope

—

PLL input clock (after predivider)

100

MHz

Time

o.5 V

3.3 V

1.2 V

VDDH Nominal

PORESET/TRST asserted

VDD Nominal

CLKIN starts toggling

VDD applied

PORESET/TRST deasserted

VDDH applied

VDDH = Nominal

VDD = Nominal

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