MNSC140CORE datasheet(16/88 Pages) FREESCALE

16 / 88 page

MSC8122 Technical Data, Rev. 13

1-6

Freescale Semiconductor

Signals/Connections

HD46

D46

ETHTXD0

Input/ Output

Output

Host Data Bus 46

Bit 46 of the DSI data bus.

System Bus Data 46

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 0

In MII and RMII modes, bit 0 of the Ethernet transmit data.

HD47

D47

ETHTXD1

Input/ Output

Output

Host Data Bus 47

Bit 47 of the DSI data bus.

System Bus Data 47

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 1

In MII and RMII modes, bit 1 of the Ethernet transmit data.

HD48

D48

ETHTXD2

Reserved

Input/ Output

Output

Input

Host Data Bus 48

Bit 48 of the DSI data bus.

System Bus Data 48

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 2

In MII mode only, bit 2 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD49

D49

ETHTXD3

Reserved

Input/ Output

Output

Input

Host Data Bus 49

Bit 49 of the DSI data bus.

System Bus Data 49

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data 3

In MII mode only, bit 3 of the Ethernet transmit data.

In RMII mode, this pin is reserved and can be left unconnected.

HD[50–53]

D[50–53]

Reserved

Input/ Output

Input

Host Data Bus 50–53

Bits 50–53 of the DSI data bus.

System Bus Data 50–53

For write transactions, the bus master drives valid data on this bus. For read transactions, the slave drives

valid data on this bus.

If the Ethernet port is enabled and multiplexed with the DSI/System bus, these pins are reserved and can

be left unconnected.

HD54

D54

ETHTX_EN

Input/ Output

Output

Host Data Bus 54

Bit 54 of the DSI data bus.

System Bus Data 54

For write transactions, the bus master drives valid data on this line. For read transactions, the slave drives

valid data on this bus.

Ethernet Transmit Data Enable

In MII and RMII modes, indicates that the transmit data is valid.

Table 1-5.

DSI, System Bus, Ethernet, and Interrupt Signals (Continued)

Signal Name

Type

Description

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